Performance potentials of compiler-directed data speculation

Compiler-directed data speculation has been implemented on Itanium systems to allow for a compiler 10 move a load across a store even when the two operations are potentially aliased This not only breaks data dependency to reduce critical path length, but also allows a load to be scheduled far apart from its uses to hide cache miss latencies. However, the effectiveness of data speculation is affected by the sophistication of alias analysis technique as well as the aggressiveness af the instruction scheduler. In general, the more sophisticated is the alias analysis technique, the less performance gain i s t o m data speculation, and the more aggressive is the instruction scheduler, the more opportunity is for data speculation. I n this paper we evaluate in various scenarios the performonce potentials of data speculation for SPEC2OOOC benchmarks. For each scenario, we determine the performance contributions of data speculation due to both critical path reduction and cache miss latency reduction. We also show interesting statistics about the effects of scheduling constraints, the percentage of critical dependencies, the impacts of cache miss latencies, and the distances behJeen the load locations before and ajier data speculation.